Microprocessors such as digital signal processors perform addition of two binary numbers, each of which can have several bits. Microprocessors available today operate on binary numbers with 4 to 64 bits. The trend has been to increase the number of bits in the binary numbers. Therefore it is expected microprocessors in the future will operate on binary numbers having even more bits.
In performing the addition of two numbers, one of the numbers, known as the augend, is stored in a first register. The other number, known as the addend, is stored in a second register. The addition process begins by adding the least significant bits of the augend and addend in a first cell of a multicell adder. A sum bit and carry bit are generated. The carry bit is added to the sum of the augend bit and the addend bit in the next cell. This process continues through as many cells as are necessary to complete the addition.
In each cell, the addition of three bits occurs: an augend bit, an addend bit, and a carry bit from the previous (if present) cell. The carry bit from the previous cell is sometimes referred to as a carry-in bit. The result of the addition of these three bits produces two bits as outputs. The two bits are a sum bit and a carry bit, sometimes referred to as a carry-out bit to distinguish it from the carry-in bit. The carry-out bit is provided to the next cell as the carry-in bit or, through some carry look-ahead or carry skip-ahead technique, is propagated to a cell location of a more significant bit. A carry-out bit from the cell having as two of its inputs the most significant bits of the registers storing the augend and addend may indicate a carry overflow condition. Since the addition process is the same in each cell, it has been the practice of microprocessor manufacturers to develop a logic circuit to perform the binary addition for one cell, and then to replicate the circuit for each cell position. The resultant multicell adder is thus a cascaded series of identical one-bit adders. These multicell adders may be used within each group of a carry-skip adder or other types of fast adders.
A well-known technique of cascading a series of one-bit adders to form a fast n-bit carry-ripple adder is to omit the final inverter used in generating the sum and carry outputs. Every other one-bit adder, or cell, is designed to operate on inverted inputs. A drawback of this technique is the necessity for additional inverters to invert the inputs of every other cell, as well as the sum output bit of the alternate cells.
Using identical circuits for each cell position necessitates inverting some of the inputs to a cell prior to performing addition, or inverting some of the outputs from a cell subsequent to performing the addition but before passing the outputs on, such as to the next cell in the cascaded series or as an output bit from the adder. Introduction of inverters increases the power consumed in performing an addition operation, and increases the time necessary for a cell to complete its addition operation. The increased time consumed is aggregated when the microprocessor performs operations that are addition intensive such as matrix multiplication, convolution or correlation.
It would be desirable to have a fast n-bit adder in which there is no need to invert any of the inputs to adder cells and the adder would generate the true sum output for each cell.